In memory systems with multiple memory devices operably coupled to a shared memory bus, it is frequently advantageous to synchronize the performance of various memory operations among the memory devices. For example, in a memory system in which multiple memory modules are connected to a single memory bus, it may be beneficial to synchronize a data transfer operation in one memory module with a termination mode in the other memory modules, so that the impedance is properly controlled for best signal quality during the data transfer operation.
One way to provide such synchronization is to provide memory systems with multiple memory devices that all have the same latencies in response to corresponding memory commands, so that a single command can be made on the command/address bus to command one of the memory devices to perform a data transfer operation (e.g., a read or a write operation) at the same time as the other devices are placed into a termination mode (e.g., by utilizing different chip select signals to indicate which memory device is the target of the read operation, and which are non-targets that should be placed in a termination mode). This approach, however, is limited to systems in which all of the memory devices on the shared memory bus have the same latency in response to a given command (e.g., in which the latency between the first memory device receiving a data transfer command and performing a corresponding data transfer operation is the same as the latency between the remaining memory devices receiving the termination mode command and entering a termination mode). Accordingly, it is desirable to provide improved methods of synchronizing memory operations and memory systems that employ the same.